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Chapter 13

DIGITAL SYSTEMS AND INFORMATION3

1-1　Information Representation4

The Digital Computer6

Beyond the Computer7

More on the Generic Computer11

1-2　Number Systems13

Binary Numbers14

Octal and Hexadecimal Numbers16

Number Ranges17

1-3　Arithmetic Operations18

Conversion from Decimal to Other Bases20

1-4　Decimal Codes23

BCD Addition24

1-5　Alphanumeric Codes25

ASCII Character Code26

Parity Bit26

1-6　Gray Codes28

1-7　Chapter Summary31

References31

Problems31

Chapter 235

COMBINATIONAL LOGIC CIRCUITS35

2-1　Binary Logic and Gates35

Binary Logic36

Logic Gates38

2-2　Boolean Algebra39

Basic Identities of Boolean Algebra42

Algebraic Manipulation44

Complement of a Function47

2-3　Standard Forms48

Minterms and Maxterms49

Sum of Products52

Product of Sums54

2-4　Two-Level Circuit Optimization54

Cost Criteria55

Map Structures56

Two-Variable Maps59

Three-Variable Maps61

2-5　Map Manipulation65

Essential Prime Implicants65

Nonessential Prime Implicants67

Product-of-Sums Optimization68

Don't-Care Conditions70

2-6　Pragmatic Two-Level Optimization72

2-7　Multiple-Level Circuit Optimization76

2-8　Other Gate Types81

2-9　Exclusive-OR Operator and Gates85

Odd Function86

2-10　High-Impedance Outputs88

2-11　Chapter Summary90

References90

Problems91

Chapter 397

COMBINATIONAL LOGIC DESIGN97

3-1　Design Procedure97

3-2　Beginning Hierarchical Design104

3-3　Technology Mapping107

3-4　Verification111

Manual Logic Analysis111

Simulation113

3-5　Combinational Functional Blocks113

3-6　Rudimentary Logic Functions115

Value-Fixing,Transferring,and Inverting115

Multiple-Bit Functions116

Enabling119

3-7　Decoding121

Decoder and Enabling Combinations124

Decoder-Based Combinational Circuits126

3-8　Encoding127

Priority Encoder129

Encoder Expansion130

3-9　Selecting131

Multiplexers131

Multiplexer-Based Combinational Circuits136

3-10 Chapter Summary138

References140

Problems140

Chapter 4149

ARITHMETIC FUNCTIONS AND HDLs149

4-1　Iterative Combinational Circuits150

4-2　Binary Adders151

Half Adder151

Full Adder152

Binary Ripple Carry Adder153

4-3　Binary Subtraction155

Complements157

Subtraction Using 2s Complement158

4-4　Binary Adder-Subtractors159

Signed Binary Numbers161

Signed Binary Addition and Subtraction163

Overflow165

4-5　Other Arithmetic Functions167

Contraction167

Incrementing169

Decrementing170

Multiplication by Constants170

Division by Constants172

Zero Fill and Extension172

4-6 Hardware Description Languages173

Hardware Description Languages173

Logic Synthesis175

4-7 HDL Representations—VHDL176

Behavioral Description186

4-8　HDL Representations—Verilog187

Behavioral Description195

4-9　Chapter Summary196

References196

Problems197

Chapter 5207

SEQUENTIAL CIRCUITS207

5-1 Sequential Circuit Definitions208

5-2 Latches210

SR and ？Latches211

D Latch214

5-3 Flip-Flops215

Master-Slave Flip-Flops216

Edge-Triggered Flip-Flop218

Standard Graphics Symbols219

Direct Inputs221

5-4 Sequential Circuit Analysis222

Input Equations223

State Table224

State Diagram227

Sequential Circuit Simulation229

5-5 Sequential Circuit Design230

Design Procedure231

Finding State Diagrams and State Tables231

State Assignment238

Designing with D Flip-Flops240

Designing with Unused States243

Verification245

5-6 Other Flip-Flop Types247

JK and T Flip-Flops247

5-7 State-Machine Diagrams and Applications250

State-Machine Diagram Model250

Constraints on Input Conditions253

Design Applications Using State-Machine Diagrams256

5-8 HDL Representation for Sequential Circuits—VHDL264

5-9 HDL Representation for Sequential Circuits—Verilog272

5-10 Chapter Summary278

References279

Problems280

Chapter 6295

SELECTED DESIGN TOPICS295

6-1　The Design Space295

Integrated Circuits296

CMOS Circuit Technology296

Technology Parameters302

6-2 Gate Propagation Delay304

6-3 Flip-Flop Timing306

6-4 Sequential Circuit Timing308

6-5 Asynchronous Interactions310

6-6 Synchronization and Metastability312

6-7 Synchronous Circuit Pitfalls318

6-8 Programmable Implementation Technologies319

Read-Only Memory322

Programmable Logic Array323

Programmable Array Logic Devices327

6-9 Chapter Summary329

References329

Problems330

Chapter 7335

REGISTERS AND REGISTER TRANSFERS335

7-1 Registers and Load Enable336

Register with Parallel Load337

7-2 Register Transfers339

7-3 Register Transfer Operations341

7-4 A Note for VHDL and Verilog Users Only344

7-5 Microoperations344

Arithmetic Microoperations345

Logic Microoperations347

Shift Microoperations349

7-6 Microoperations on a Single Register350

Multiplexer-Based Transfers350

Shift Registers353

Ripple Counter357

Synchronous Binary Counters359

Other Counters363

7-7　Register-Cell Design366

7-8　Multiplexer and Bus-Based Transfers for Multiple Registers372

Three-State Bus374

7-9　Serial Transfer and Microoperations375

Serial Addition377

7-10　Control of Register Transfers378

Design Procedure380

7-11　HDL Representation for Shift Registers and Counters—VHDL395

7-12　HDL Representation for Shift Registers and Counters—Verilog398

7-13 Microprogrammed Control399

7-14 Chapter Summary402

References402

Problems402

Chapter 8413

MEMORY BASICS413

8-1 Memory Definitions413

8-2 Random-Access Memory414

Write and Read Operations416

Timing Waveforms417

Properties of Memory419

8-3 SRAM Integrated Circuits419

Coincident Selection422

8-4 Array of SRAM ICs425

8-5 DRAM ICs429

DRAM Cell429

DRAM Bit Slice431

8-6 DRAM Types435

Synchronous DRAM(SDRAM)436

Double-Data-Rate SDRAM(DDR SDRAM)439

RAMBUS？ DRAM(RDRAM)439

8-7　Arrays of Dynamic RAM ICs440

8-8 Chapter Summary441

References441

Problems441

Chapter 9443

COMPUTER DESIGN BASICS443

9-1 Introduction444

9-2 Datapaths444

9-3 The Arithmetic/Logic Unit447

Arithmetic Circuit448

Logic Circuit450

Arithmetic/Logic Unit451

9-4 The Shifter453

Barrel Shifter454

9-5 Datapath Representation455

9-6 The Control Word458

9-7 A Simple Computer Architecture464

Instruction Set Architecture464

Storage Resources465

Instruction Formats466

Instruction Specifications468

9-8 Single-Cycle Hardwired Control471

Instruction Decoder472

Sample Instructions and Program474

Single-Cycle Computer Issues477

9-9 Multiple-Cycle Hardwired Control478

Sequential Control Design482

9-10 Chapter Summary489

References490

Problems490

Chapter 10497

INSTRUCTION SET ARCHITECTURE497

10-1 Computer Architecture Concepts497

Basic Computer Operation Cycle498

Register Set499

10-2 Operand Addressing499

Three-Address Instructions500

Two-Address Instructions501

One-Address Instructions501

Zero-Address Instructions502

Addressing Architectures503

10-3 Addressing Modes506

Implied Mode507

Immediate Mode507

Register and Register-Indirect Modes508

Direct Addressing Mode508

Indirect Addressing Mode510

Relative Addressing Mode510

Indexed Addressing Mode511

Summary of Addressing Modes511

10-4 Instruction Set Architectures513

10-5 Data-Transfer Instructions514

Stack Instructions515

Independent versus Memory-Mapped I/O517

10-6 Data-Manipulation Instructions518

Arithmetic Instructions518

Logical and Bit-Manipulation Instructions519

Shift Instructions520

10-7 Floating-Point Computations522

Arithmetic Operations523

Biased Exponent524

Standard Operand Format525

10-8 Program Control Instructions527

Conditional Branch Instructions528

Procedure Call and Return Instructions530

10-9 Program Interrupt531

Types of Interrupts533

Processing External Interrupts534

10-10 Chapter Summary535

References536

Problems537

Chapter 11543

RISC AND CISC CENTRAL PROCESSING UNITS543

11-1 Pipelined Datapath544

Execution of Pipeline Microoperations548

11-2 Pipdined Control549

Pipeline Programming and Performance551

11-3 The Reduced Instruction Set Computer553

Instruction Set Architecture554

Addressing Modes557

Datapath Organization557

Control Organization560

Data Hazards563

Control Hazards570

11-4 The Complex Instruction Set Computer574

ISA Modifications575

Datapath Modifications577

Control Unit Modifications577

Microprogrammed Control579

Microprograms for Complex Instructions582

11-5 More on Design586

Advanced CPU Concepts586

Recent Architectural Innovations589

11-6 Chapter Summary592

References593

Problems593

Chapter 12597

INPUT-OUTPUT AND COMMUNICATION597

12-1　Computer I/O597

12-2　Sample Peripherals598

Keyboard598

Hard Drive599

Liquid Crystal Display Screen601

I/O Transfer Rates604

12-3　I/O Interfaces604

I/O Bus and Interface Unit605

Example of I/O Interface606

Strobing608

Handshaking609

12-4　Serial Communication611

Synchronous Transmission612

The Keyboard Revisited612

A Packet-Based Serial I/O Bus613

12-5 Modes of Transfer617

Example of Program-Controlled Transfer618

Interrupt-Initiated Transfer620

12-6 Priority Interrupt620

Daisy Chain Priority621

Parallel Priority Hardware623

12-7　Direct Memory Access624

DMA Controller625

DMA Transfer627

12-8 Chapter Summary628

References628

Problems629

Chapter 13633

MEMORY SYSTEMS633

13-1　Memory Hierarchy633

13-2　Locality of Reference636

13-3　Cache Memory638

Cache Mappings640

Line Size645

Cache Loading647

Write Methods647

Integration of Concepts648

Instruction and Data Caches651

Multiple-Level Caches651

13-4　Virtual Memory652

Page Tables654

Translation Lookaside Buffer656

Virtual Memory and Cache658

13-5　Chapter Summary658

References659

Problems659

INDEX663