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计算机体系结构习题与解答 英文版PDF|Epub|txt|kindle电子书版本网盘下载
- （美）Nicholas Carter著 著
- 出版社： 北京：机械工业出版社
- ISBN：7111104188
- 出版时间：2002
- 标注页数：306页
- 文件大小：16MB
- 文件页数：315页
- 主题词：暂缺
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图书目录
CHAPTER 1 Introduction1
1.1 Purpose of This Book1
1.2 Background Assumed1
1.3 Material Covered1
1.4 Chapter Objectives2
1.5 Technological Trends2
1.6 Measuring Performance3
1.7 Speedup6
1.8 Amdahl's Law6
1.9 Summary7
Solved Problems8
CHAPTER 2 Data Representations and Computer Arithmetic16
2.1 Objectives16
2.2 From Electrons to Bits16
2.3 Binary Representation of Positive Integers18
2.4 Arithmetic Operations on Positive Integers19
2.5 Negative Integers23
2.6 Floating-Point Numbers28
2.7 Summary35
Solved Problems36
CHAPTER 3 Computer Organization45
3.1 Objectives45
3.2 Introduction45
3.3 Programs46
3.4 Operating Systems50
3.5 Computer Organization53
3.6 Summary57
Solved Problems57
4.1 Objectives63
4.2 Introduction63
CHAPTER 4 Programming Models63
4.3 Types of Instructions65
4.4 Stack-Based Architectures70
4.5 General-Purpose Register Architectures78
4.6 Comparing Stack-Based and General-Purpose Register Architectures83
4.7 Using Stacks to Implement Procedure Calls84
4.8 Summary86
Solved Problems87
CHAPTER 5 Processor Design94
5.1 Objectives94
5.2 Introduction94
5.3 Instruction Set Architecture95
5.4 Processor Microarchitecture103
5.5 Summary107
Solved Problems108
6.2 Introduction115
CHAPTER 6 Pipelining115
6.1 Objectives115
6.3 Pipelining116
6.4 Instruction Hazards and Their Impact on Throughput120
6.5 Predicting Execution Time in Pipelined Processors126
6.6 Result Forwarding(Bypassing)130
6.7 Summary133
Solved Problems134
CHAPTER 7 Instruction-Level Parallelism144
7.1 Objectives144
7.2 Introduction144
7.3 What is Instruction-Level Parallelism?146
7.4 Limitations of Instruction-Level Parallelism147
7.5 Superscalar Processors149
7.6 In-Order versus Out-of-Order Execution149
7.7 Register Renaming153
7.8 VLIW Processors156
7.9 Compilation Techniques for Instruction-Level Parallelism159
7.10 Summary162
Solved Problems164
CHAPTER 8 Memory Systems175
8.1 Objectives175
8.2 Introduction175
8.3 Latency,Throughput,and Bandwidth176
8.4 Memory Hierarchies179
8.5 Memory Technologies183
8.6 Summary190
Solved Problems191
CHAPTER 9 Caches198
9.1 Objectives198
9.2 Introduction198
9.3 Data Caches,Instruction Caches,and Unified Caches199
9.4 Describing Caches200
9.5 Capacity201
9.6 Line Length201
9.7 Associativity203
9.8 Replacement Policy208
9.9 Write-Back versus Write-Through Caches210
9.10 Cache Implementations212
9.11 Tag Arrays212
9.12 Hit/Miss Logic214
9.13 Data Arrays214
9.14 Categorizing Cache Misses216
9.15 Multilevel Caches217
9.16 Summary219
Solved Problems219
10.2 Introduction229
10.1 Objectives229
CHAPTER 10 Virtual Memory229
10.3 Address Translation230
10.4 Demand Paging versus Swapping233
10.5 Page Tables234
10.6 Translation Lookaside Buffers239
10.7 Protection243
10.8 Caches and Virtual Memory245
10.9 Summary247
Solved Problems248
CHAPTER 11 I/O255
11.1 Objectives255
11.2 Introduction255
11.3 I/O Buses256
11.4 Interrupts258
11.5 Memory-Mapped I/O262
11.6 Direct Memory Access264
11.7 I/O Devices265
11.8 Disk Systems266
11.9 Summary270
Solved Problems271
CHAPTER 12 Multiprocessors279
12.1 Objectives279
12.2 Introduction279
12.3 Speedup and Performance280
12.4 Multiprocessor Systems282
12.5 Message-Passing Systems285
12.6 Shared-Memory Systems286
12.7 Comparing Message-Passing and Shared Memory293
12.8 Summary294
Solved Problems295
INDEX303