计算机体系结构 量化研究方法 英文版·第3版PDF|Epub|txt|kindle电子书版本网盘下载

计算机体系结构 量化研究方法 英文版·第3版PDF格式电子书版下载

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Index1

References1

B.1 Chapter 1 Solutions2

Introduction2

Appendix B Solutions to Selected Exercises2

A.1 Introduction2

Appendix A Pipelining:Basic and Intermediate Concepts2

Chapter 1 Fundamentals of Computer Design2

1.1 Introduction2

1.2 The Changing Face of Computing and the Task of the Computer Designer4

B.2 Chapter 2 Solutions7

A.2 The Major Hurdle of Pipelining—Pipeline Hazards11

1.3 Technology Trends11

B.3 Chapter 3 Solutions11

1.4 Cost,Price,and Their Trends14

B.4 Chapter 4 Solutions16

B.5 Chapter 5 Solutions21

1.5 Measuring and Reporting Performance24

B.6 Chapter 6 Solutions25

A.3 How Is Pipelining Implemented？26

B.7 Chapter 7 Solutions29

B.8 Chapter 8 Solutions30

B.9 Appendix A Solutions35

A.4 What Makes Pipelining Hard to Implement？37

1.6 Quantitative Principles of Computer Design39

A.5 Extending the MIPS Pipeline to Handle Multicycle Operations47

1.7 Putting It All Together:Performance and Price-Performance48

1.8 Another View:Power Consumption and Efficiency as the Metric56

A.6 Putting It All Together:The MIPS R4000 Pipeline57

1.9 Fallacies and Pitfalls57

1.10 Concluding Remarks65

A.7 Another View:The MIPS R4300 Pipeline66

1.11 Historical Perspective and References67

A.8 Crosscutting Issues67

Exercises74

A.9 Fallacies and Pitfalls77

A.11 Historical Perspective and References78

A.10 Concluding Remarks78

Exercises81

Chapter 2 Instruction Set Principles and Examples90

2.1 Introduction90

2.2 Classifying Instruction Set Architectures92

2.3 Memory Addressing95

2.4 Addressing Modes for Signal Processing101

2.5 Type and Size of Operands104

2.6 Operands for Media and Signal Processing105

2.7 Operations in the Instruction Set108

2.8 Operations for Media and Signal Processing109

2.9 Instructions for Control Flow111

2.10 Encoding an Instruction Set117

2.11 Crosscutting Issues:The Role of Compilers120

2.12 Putting It All Together:The MIPS Architecture129

2.13 Another View:The Trimedia TM32 CPU136

2.14 Fallacies and Pitfalls142

2.15 Concluding Remarks147

2.16 Historical Perspective and References148

Exercises161

3.1 Instruction-Level Parallelism:Concepts and Challenges172

Chapter 3 Instruction-Level Parallelism and Its Dynamic Exploitation172

3.2 Overcoming Data Hazards with Dynamic Scheduling181

3.3 Dynamic Scheduling:Examples and the Algorithm189

3.4 Reducing Branch Costs with Dynamic Hardware Prediction196

3.5 High-Performance Instruction Delivery209

3.6 Taking Advantage of More ILP with Multiple Issue215

3.7 Hardware-Based Speculation224

3.8 Studies of the Limitations of ILP240

3.9 Limitations on ILP for Realizable Processors253

3.10 Putting It All Together:The P6 Microarchitecture259

3.11 Another View:Thread-Level Parallelism272

3.12 Crosscutting Issues:Using an ILP Data Path to Exploit TLP273

3.13 Fallacies and Pitfalls273

3.14 Concluding Remarks276

3.15 Historical Perspective and References280

Exercises288

Chapter 4 Exploiting Instruction-Level Parallelism with Software Approaches304

4.1 Basic Compiler Techniques for Exposing ILP304

4.2 Static Branch Prediction313

4.3 Static Multiple Issue:The VLIW Approach315

4.4 Advanced Compiler Support for Exposing and Exploiting ILP319

4.5 Hardware Support for Exposing More Parallelism at Compile Time340

4.6 Crosscutting Issues:Hardware versus Software Speculation Mechanisms350

4.7 Putting It All Together:The Intel IA-64 Architecture and (?)tanium Processor351

4.8 AnotherView:ILP in the Embedded and Mobile Markets363

4.9 Fallacies and Pitfalls370

4.10 Concluding Remarks372

4.11 Historical Perspective and References373

Exercises378

Chapter 5 Memory Hierarchy Design390

5.1 Introduction390

5.2 Review of the ABCs of Caches392

5.3 Cache Performance406

5.4 Reducing Cache Miss Penalty413

5.5 Reducing Miss Rate423

5.6 Reducing Cache Miss Penalty or Miss Rate via Parallelism435

5.7 Reducing Hit Time443

5.8 Main Memory and Organizations for Improving Performance448

5.9 Memory Technology454

5.10 Virtual Memory460

5.11 Protection and Examples of Virtual Memory469

5.12 Crosscutting Issues:The Design of Memory Hierarchies478

5.13 Putting It All Together:Alpha 21264 Memory Hierarchy482

5.14 Another View:The Emotion Engine of the Sony Playstation 2490

5.15 Another View:The Sun Fire 6800 Server494

5.16 Fallacies and Pitfalls498

5.17 Concluding Remarks504

5.18 Historical Perspective and References504

Exercises513

Chapter 6 Multiprocessors and Thread-Level Parallelism528

6.1 Introduction528

6.2 Characteristics of Application Domains540

6.3 Symmetric Shared-Memory Architectures549

6.4 Performance of Symmetric Shared-Memory Multiprocessors560

6.5 Distributed Shared-Memory Architectures576

6.6 Performance of Distributed Shared-Memory Multiprocessors584

6.7 Synchronization590

6.8 Models of Memory Consistency:An Introduction605

6.9 Multithreading:Exploiting Thread-Level Parallelism within a Processor608

6.10 Crosscutting Issues615

6.11 Putting It All Together:Sun s Wildfire Prototype622

6.12 Another View:Multithreading in a Commercial Server635

6.13 Another View:Embedded Multiprocessors636

6.14 Fallacies and Pitfalls637

6.15 Concluding Remarks643

6.16 Historical Perspective and References649

Exercises665

Chapter 7 Storage Systems678

7.1 Introduction678

7.2 Types of Storage Devices679

7.3 Buses—Connecting I/O Devices to CPU/Memory692

7.4 Reliability,Availability,and Dependability702

7.5 RAID:Redundant Arrays of Inexpensive Disks705

7.6 Errors and Failures in Real Systems710

7.7 I/O Performance Measures716

7.8 A Little Queuing Theory720

7.9 Benchmarks of Storage Performance and Avai(?)ability731

7.10 Crosscutting Issues737

7.11 Designing an I/O System in Five Easy Pieces741

7.12 Putting It All Together:EMC Symmetrix and Celerra754

7.13 Another View:Sanyo VPC-SX5O0 Digital Camera760

7.14 Fallacies and Pitfalls763

7.15 Concluding Remarks769

7.16 Historical Perspective and References770

Exercises778

Chapter 8 Interconnection Networks and Clusters788

8.1 Introduction788

8.2 A Simple Network793

8.3 Interconnection Network Media802

8.4 Connecting More Than Two Computers805

8.5 Network Topology814

8.6 Practical Issues for Commercial Interconnection Networks821

8.7 Examples of Interconnection Networks825

8.8 Internetworking830

8.9 Crosscutting Issues for Interconnection Networks834

8.10 Clusters838

8.11 Designing a Cluster843

8.12 Putting It All Together:The Google Cluster of PCs855

8.13 Another View:Inside a Cell Phone862

8.14 Fallacies and Pitfalls867

8.15 Concluding Remarks870

8.16 Historical Perspective and References871

Exercises877