Verilog HDL高级数字设计 英文版PDF|Epub|txt|kindle电子书版本网盘下载

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1　Introduction to Digital Design Methodology1

1.1 Design Methodology—An Introduction2

1.1.1 Design Specification4

1.1.2 Design Partition4

1.1.3 Design Entry4

1.1.4 Simulation and Functional Verification5

1.1.5 Design Integration and Verification6

1.1.6 Presynthesis Sign-Off6

1.1.7 Gate-Level Synthesis and Technology Mapping6

1.1.8 Postsynthesis Design Validation7

1.1.9 Postsynthesis Timing Verification8

1.1.10 Test Generation and Fault Simulation8

1.1.11 Placement and Routing8

1.1.12 Physical and Electrical Design Rule Checks9

1.1.13 Parasitic Extraction9

1.1.14 Design Sign-Off9

1.2 IC Technology Options9

1.3 Overview11

References11

2 Review of Combinational Logic Design13

2.1 Combinational Logic and Boolean Algebra13

2.1.1 ASIC Library Cells13

2.1.2 Boolean Algebra16

2.1.3 DeMorgan's Laws18

2.2 Theorems for Boolean Algebraic Minimization18

2.3 Representation of Combinational Logic21

2.3.1 Sum-of-Products Representation23

2.3.2 Product-of-Sums Representation26

2.4 Simplification of Boolean Expressions27

2.4.1 Simplification with Exclusive-Or36

2.4.2 Karnaugh Maps(SOP Form)36

2.4.3 Karnaugh Maps(POS Form)39

2.4.4 Karnaugh Maps and Don't-Cares40

2.4.5 Extended Karnaugh Maps41

2.5 Glitches and Hazards42

2.5.1 Elimination of Static Hazards(SOP Form)45

2.5.2 Summary:Elimination of Static Hazards in Two-Level Circuits48

2.5.3 Static Hazards in Multilevel Circuits49

2.5.4 Summary:Elimination of Static Hazards in Multilevel Circuits52

2.5.5 Dynamic Hazards52

2.6 Building Blocks for Logic Design55

2.6.1 NAND-NOR Structures55

2.6.2 Multiplexers60

2.6.3 Demultiplexers61

2.6.4 Encoders62

2.6.5 Priority Encoder63

2.6.6 Decoder64

2.6.7 Priority Decoder66

References67

Problems67

3 Fundamentals of Sequential Logic Design69

3.1 Storage Elements69

3.1.1 Latches70

3.1.2 Transparent Latches71

3.2 Flip-Flops71

3.2.1 D-Type Flip-Flop71

3.2.2 Master-Slave Flip-Flop73

3.2.3 J-K Flip-Flops75

3.2.4 T Flip-Flop75

3.3 Busses and Three-State Devices76

3.4 Design of Sequential Machines80

3.5 State-Transition Graphs82

3.6 Design Example:BCD to Excess-3 Code Converter84

3.7 Serial-Line Code Converter for Data Transmission90

3.7.1 Design Example:A Mealy-Type FSM for Serial Line-Code Conversion92

3.7.2 Design Example:A Moore-Type FSM for Serial Line-Code Conversion93

3.8 State Reduction and Equivalent States95

References99

Problems100

4 Introduction to Logic Design with Verilog103

4.1 Structural Models of Combinational Logic104

4.1.1 Verilog Primitives and Design Encapsulation104

4.1.2 Verilog Structural Models107

4.1.3 Module Ports108

4.1.4 Some Language Rules108

4.1.5 ToP-Down Design and Nested Modules109

4.1.6 Design Hierarchy and Source-Code Organization111

4.1.7 Vectors in Verilog113

4.1.8 Structural Connectivity114

4.2 Logic System,Design Verification,and Test Methodology118

4.2.1 Four-Value Logic and Signal Resolution in Verilog119

4.2.2 Test Methodology120

4.2.3 Signal Generators for Testbenches123

4.2.4 Event-Driven Simulation125

4.2.5 Testbench Template125

4.2.6 Sized Numbers126

4.3 Propagation Delay126

43.1 Inertial Delay129

4.3.2 Transport Delay131

4.4 Truth Table Models of Combinational and Sequential Logic with Verilog131

References138

Problems138

5 Logic Design with Behavioral Models of Combinational and Sequential Logic141

5.1 Behavioral Modeling141

5.2 A Brief Look at Data Types for Behavioral Modeling143

5.3 Boolean Equation-Based Behavioral Models of Combinational Logic143

5.4 Propagation Delay and Continuous Assignments146

5.5 Latches and Level-Sensitive Circuits in Verilog148

5.6 Cyclic Behavioral Models of Flip-Flops and Latches150

5.7 Cyclic Behavior and Edge Detection152

5.8 A Comparison of Styles for Behavioral Modeling154

5.8.1 Continuous Assignment Models154

5.8.2 Dataflow/RTL Models156

5.8.3 Algorithm-Based Models160

5.8.4 Naming Conventions:A Matter of Style161

5.8.5 Simulation with Behavioral Models162

5.9 Behavioral Models of Multiplexers,Encoders,and Decoders162

5.10 Dataflow Models of a Linear-Feedback Shift Register171

5.11 Modeling Digital Machines with Repetitive Algorithms173

5.11.1 Intellectual Property Reuse and Parameterized Models178

5.11.2 Clock Generators180

5.12 Machines with Multicycle Operations182

5.13 Design Documentation with Functions and Tasks:Legacy or Lunacy?183

5.13.1 Tasks184

5.13.2 Functions185

5.14 Algorithmic State Machine Charts for Behavioral Modeling187

5.15 ASMD Charts191

5.16 Behavioral Models of Counters,Shift Registers,and Register Files195

5.16.1 Counters195

5.16.2 Shift Registers202

5.16.3 Register Files and Arrays of Registers(Memories)206

5.17 Switch Debounce,Metastability,and Synchronizers for Asynchronous Signals208

5.18 Design Example:Keypad Scanner and Encoder214

References223

Problems223

6 Synthesis of Combinational and Sequential Logic235

6.1 Introduction to Synthesis236

6.1.1 Logic Synthesis237

6.1.2 RTL Synthesis245

6.1.3 High-Level Synthesis246

6.2 Synthesis of Combinational Logic247

6.2.1 Synthesis of Priority Structures252

6.2.2 Exploiting Logical Don't-Care Conditions253

6.2.3 ASIC Cells and Resource Sharing258

6.3 Synthesis of Sequential Logic with Latches260

6.3.1 Accidental Synthesis of Latches262

6.3.2 Intentional Synthesis of Latches266

6.4 Synthesis of Three-State Devices and Bus Interfaces269

6.5 Synthesis of Sequential Logic with Flip-Flops272

6.6 Synthesis of Explicit State Machines275

6.6.1 Synthesis of a BCD-to-Excess-3 Code Converter276

6.6.2 Design Example:Synthesis of a Mealy-Type NRZ-to-Manchester Line Code Converter281

6.6.3 Design Example:Synthesis of a Moore-Type NRZ-to-Manchester Line Code Converter283

6.6.4 Design Example:Synthesis of a Sequence Recognizer284

6.7 Registered Logic292

6.8 State Encoding300

6.9 Synthesis of Implicit State Machines,Registers,and Counters302

6.9.1 Implicit State Machines303

6.9.2 Synthesis of Counters304

6.9.3 Synthesis of Registers305

6.10 Resets309

6.11 Synthesis of Gated Clocks and Clock Enables313

6.12 Anticipating the Results of Synthesis314

6.12.1 Synthesis of Data Types314

6.12.2 Operator Grouping314

6.12.3 Expression Substitution315

6.13 Synthesis of Loops318

6.13.1 Static Loops without Embedded Timing Controls318

6.13.2 Static Loops with Embedded Timing Controls321

6.13.3 Nonstatic Loops without Embedded Timing Controls324

6.13.4 Nonstatic Loops with Embedded Timing Controls326

6.13.5 State-Machine Replacements for Unsynthesizable Loops329

6.14 Design Traps to Avoid334

6.15 Divide and Conquer:Partitioning a Design335

References336

Problems337

7 Design and Synthesis of Datapath Controllers345

7.1 Partitioned Sequential Machines345

7.2 Design Example:Binary Counter347

7.3 Design and Synthesis of a RISC Stored-Program Machine353

7.3.1 RISC SPM:Processor355

7.3.2 RISC SPM:ALU355

7.3.3 RISC SPM:Controller355

7.3.4 RISC SPM:Instruction Set356

7.3.5 RISC SPM:Controller Design358

7.3.6 RISC SPM:Program Execution372

7.4 Design Example:UART375

7.4.1 UART Operation376

7.4.2 UART Transmitter377

7.4.3 UART Receiver387

References399

Problems400

8 Programmable Logic and Storage Devices415

8.1 Programmable Logic Devices417

8.2 Storage Devices417

8.2.1 Read-Only Memory(ROM)418

8.2.2 Programmable ROM(PROM)420

8.2.3 Erasable ROMs421

8.2.4 ROM-Based Implementation of Combinational Logic423

8.2.5 Verilog System Tasks for ROMs423

8.2.6 Comparison of ROMs426

8.2.7 ROM-Based State Machines426

8.2.8 Flash Memory430

8.2.9 Static Random Access Memory(SRAM)430

8.2.10 Ferroelectric Nonvolatile Memory452

8.3 Programmable Logic Array(PLA)454

8.3.1 PLA Minimization457

8.3.2 PLA Modeling459

8.4 Programmable Array Logic(PAL)463

8.5 Programmability of PLDs464

8.6 Complex PLDs(CPLDs)465

8.7 Field-Programmable Gate Arrays466

8.7.1 The Role of FPGAs in the ASIC Market467

8.7.2 FPGA Technologies469

8.7.3 XILINX Virtex FPGAs470

8.8 Embeddable and Programmable IP Cores for a System-on-a-Chip(SoC)470

8.9 Verilog-Based Design Flows for FPGAs472

8.10 Synthesis with FPGAs473

References476

Related Web Sites476

Problems and FPGA-Based Design Exercises476

9 Algorithms and Architectures for Digital Processors515

9.1 Algorithms,Nested-Loop Programs,and Data Flow Graphs516

9.2 Design Example:Halftone Pixel Image Converter519

9.2.1 Baseline Design for a Halftone Pixel Image Converter522

9.2.2 NLP-Based Architectures for the Halftone Pixel Image Converter526

9.2.3 Minimum Concurrent Processor Architecture for a Halftone Pixel Image Converter532

9.2.4 Halftone Pixel Image Converter:Design Tradeoffs547

9.2.5 Architectures for Dataflow Graphs with Feedback547

9.3 Digital Filters and Signal Processors554

9.3.1 Finite-Duration Impulse Response Filter557

9.3.2 Digital Filter Design Process558

9.3.3 Infinite-Duration Impulse Response Filter563

9.4 Building Blocks for Signal Processors566

9.4.1 Integrators(Accumulators)566

9.4.2 Differentiators570

9.4.3 Decimation and Interpolation Filters570

9.5 Pipelined Architectures576

9.5.1 Design Example:Pipelined Adder579

9.5.2 Design Example:Pipelined FIR Filter583

9.6 Circular Buffers586

9.7 Asynchronous FIFOs—Synchronization across Clock Domains589

9.7.1 Simplified Asynchronous FIFO590

9.7.2 Clock Domain Synchronization for an Asynchronous FIFO599

References619

Problems620

10 Architectures for Arithmetic Processors627

10.1 Number Representation627

10.1.1 Signed Magnitude Representation of Negative Integers628

10.1.2 Ones Complement Representation of Negative Integers629

10.1.3 Twos Complement Representation of Positive and Negative Integers630

10.1.4 Representation of Fractions632

10.2 Functional Units for Addition and Subtraction632

10.2.1 Ripple-Carry Adder632

10.2.2 Carry Look-Ahead Adder633

10.2.3 Overflow and Underflow638

10.3 Functional Units for Multiplication638

10.3.1 Combinational(Parallel)Binary Multiplier639

10.3.2 Sequential Binary Multiplier642

10.3.3 Sequential Multiplier Design:Hierarchical Decomposition644

10.3.4 STG-Based Controller Design646

10.3.5 Efficient STG-Based Sequential Binary Multiplier652

10.3.6 ASMD-Based Sequential Binary Multiplier658

10.3.7 Efficient ASMD-Based Sequential Binary Multiplier664

10.3.8 Summary of ASMD-Based Datapath and Controller Design669

10.3.9 Reduced-Register Sequential Multiplier670

10.3.10 Implicit-State-Machine Binary Multiplier675

10.3.11 Booth's Algorithm Sequential Multiplier687

10.3.12 Bit-Pair Encoding702

10.4 Multiplication of Signed Binary Numbers710

10.4.1 Product of Signed Numbers:Negative Multiplicand,Positive Multiplier710

10.4.2 Product of Signed Numbers:Positive Multiplicand,Negative Multiplier710

10.4.3 Product of Signed Numbers:Negative Multiplicand,Negative Multiplier710

10.5 Multiplication of Fractions711

10.5.1 Signed Fractions:Positive Multiplicand,Positive Multiplier714

10.5.2 Signed Fractions:Negative Multiplicand,Positive Multiplier714

10.5.3 Signed Fractions:Positive Multiplicand,Negative Multiplier714

10.5.4 Signed Fractions:Negative Multiplicand,Negative Multiplier715

10.6 Functional Units for Division715

10.6.1 Division of Unsigned Binary Numbers716

10.6.2 Efficient Division of Unsigned Binary Numbers724

10.6.3 Reduced-Register Sequential Divider734

10.6.4 Division of Signed(2s Complement)Binary Numbers739

10.6.5 Signed Arithmetic739

References742

Problems742

11 Postsynthesis Design Tasks749

11.1 Postsynthesis Design Validation749

11.2 Postsynthesis Timing Verification753

11.2.1 Static Timing Analysis755

11.2.2 Timing Specifications757

11.2.3 Factors That Affect Timing760

11.3 Elimination of ASIC Timing Violations766

11.4 False Paths767

11.5 System Tasks for Timing Verification769

11.5.1 Timing Check:Setup Condition770

11.5.2 Timing Check:Hold Condition770

11.5.3 Timing Check:Setup and Hold Conditions771

11.5.4 Timing Check:Pulsewidth Constraint773

11.5.5 Timing Check:Signal Skew Constraint773

11.5.6 Timing Check:Clock Period774

11.5.7 Timing Check:Recovery Time774

11.6 Fault Simulation and Manufacturing Tests775

11.6.1 Circuit Defects and Faults776

11.6.2 Fault Detection and Testing780

11.6.3 D-Notation782

11.6.4 Automatic Test Pattern Generation for Combinational Circuits786

11.6.5 Fault Coverage and Defect Levels788

11.6.6 Test Generation for Sequential Circuits788

11.7 Fault Simulation792

11.7.1 Fault Collapsing793

11.7.2 Serial Fault Simulation793

11.7.3 Parallel Fault Simulation794

11.7.4 Concurrent Fault Simulation794

11.7.5 Probabilistic Fault Simulation794

11.8 JTAG Ports and Design for Testability794

11.8.1 Boundary Scan and JTAG Ports795

11.8.2 JTAG Modes of Operation796

11.8.3 JTAG Registers798

11.8.4 JTAG Instructions800

11.8.5 TAP Architecture801

11.8.6 TAP Controller State Machine803

11.8.7 Design Example:Testing with JTAG807

11.8.8 Design Example:Built-In Self-Test830

References845

Problems845

A Verilog Primitives851

A.1 Multiinput Combinational Logic Gates851

A.2 Multioutput Combinational Gates853

A.3 Three-State Logic Gates854

A.4 MOS Transistot Switches855

A.5 MOS Pull-Up/Pull-Down Gates860

A.6 MOS Bidirectional Switches860

B Verilog Keywords863

C Verilog Data Types865

C.1 Nets865

C.2 Register Variables866

C.3 Constants870

C.4 Referencing Arrays of Nets or Regs871

D Verilog Operators873

D.1 Arithmetic Operators873

D.2 Bitwise Operators875

D.3 Reduction Operators875

D.4 Logical Operators876

D.5 Relational Operators877

D.6 Shift Operators878

D.7 Conditional Operator878

D.8 Concatenation Operator879

D.9 Expressions and Operands880

D.10 Operator Precedence880

D.11 Arithmetic with Signed Data Types881

D.12 Signed Literal Integers882

D.13 System Functions for Sign Conversion882

2.1.1 Assignment Width Extension883

E Verilog Language Formal Syntax885

F Verilog Language Formal Syntax887

F.1 Source text887

F.2 Declarations890

F.3 Primitive instances894

F.4 Module and generated instantiation895

F.5 UDP declaration and instantiation896

F.6 Behavioral statements897

F.7 Specify section901

F.8 Expressions905

F.9 General909

G Additional Features of Verilog913

G.1 Arrays of Primitives913

G.2 Arrays of Modules913

G.3 Hierarchical Dereferencing914

G.4 Parameter Substitution915

G.5 Procedural Continuous Assignment916

G.6 Intra-Assignment Delay917

G.7 Indeterminate Assignment and Race Conditions918

G.8 wait Statement921

G.9 fork...join Statement922

G.10 Named(Abstract)Events922

G.11 Constructs Supported by Synthesis Tools923

H Flip-Flop and Latch Types925

I Verilog-2001,2005927

I.1 ANSI C Style Changes927

I.2 Code Management930

I.3 Support for Logic Modeling933

I.4 Support for Arithmetic934

I.5 Sensitivity List for Event Control940

I.6 Sensitivity List for Combinational Logic940

I.7 Parameters942

I.8 Instance Generation944

J Programming Language Interface949

K Web sites951

L Web-Based Resources953

Index955