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计算机体系结构 量化研究方法 英文版 第5版PDF|Epub|txt|kindle电子书版本网盘下载
- (美)亨尼西等著 著
- 出版社: 北京:机械工业出版社
- ISBN:9787111364580
- 出版时间:2012
- 标注页数:822页
- 文件大小:222MB
- 文件页数:852页
- 主题词:计算机体系结构-英文
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图书目录
Chapter 1 Fundamentals of Quantitative Design and Analysis2
1.1 Introduction2
1.2 Classes of Computers5
1.3 Defining Computer Architecture11
1.4 Trends in Technology17
1.5 Trends in Power and Energy in Integrated Circuits21
1.6 Trends in Cost27
1.7 Dependability33
1.8 Measuring, Reporting, and Summarizing Performance36
1.9 Quantitative Principles of Computer Design44
1.10 Putting It All Together: Performance, Price, and Power52
1.11 Fallacies and Pitfalls55
1.12 Concluding Remarks59
1.13 Historical Perspectives and References61
Case Studies and Exercises by Diana Franklin61
Chapter 2 Memory Hierarchy Design72
2.1 Introduction72
2.2 Ten Advanced Optimizations of Cache Performance78
2.3 Memory Technology and Optimizations96
2.4 Protection: Virtual Memory and Virtual Machines105
2.5 Crosscutting Issues: The Design of Memory Hierarchies112
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-A8 and Intel Core i7113
2.7 Fallacies and Pitfalls125
2.8 Concluding Remarks: Looking Ahead129
2.9 Historical Perspective and References131
Case Studies and Exercises by Norman P. Jouppi,Naveen Muralimanohar, and Sheng Li131
Chapter 3 Instruction-Level Parallelism and Its Exploitation148
3.1 Instruction-Level Parallelism: Concepts and Challenges148
3.2 Basic Compiler Techniques for Exposing ILP156
3.3 Reducing Branch Costs with Advanced Branch Prediction162
3.4 Overcoming Data Hazards with Dynamic Scheduling167
3.5 Dynamic Scheduling: Examples and the Algorithm176
3.6 Hardware-Based Speculation183
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling192
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, andSpeculation197
3.9 Advanced Techniques for Instruction Delivery and Speculation202
3.10 Studies of the Limitations of ILP213
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System221
3.12 Multithreading: Exploiting Thread-Level Parallelism to ImproveUniprocessor Throughput223
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-A8233
3.14 Fallacies and Pitfalls241
3.15 Concluding Remarks: What's Ahead?245
3.16 Historical Perspective and References247
Case Studies and Exercises by Jason D. Bakos and Robert P Colwell247
Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures262
4.1 Introduction262
4.2 Vector Architecture264
4.3 SIMD Instruction Set Extensions for Multimedia282
4.4 Graphics Processing Units288
4.5 Detecting and Enhancing Loop-Level Parallelism315
4.6 Crosscutting Issues322
4.7 Putting It All Together: Mobile versus Server GPUs and Tesla versus Core i7323
4.8 Fallacies and Pitfalls330
4.9 Concluding Remarks332
4.10 Historical Perspective and References334
Case Study and Exercises by Jason D. Bakos334
Chapter 5 Thread-Level Parallelism344
5.1 Introduction344
5.2 Centralized Shared-Memory Architectures351
5.3 Performance of Symmetric Shared-Memory Multiprocessors366
5.4 Distributed Shared-Memory and Directory-Based Coherence378
5.5 Synchronization: The Basics386
5.6 Models of Memory Consistency: An Introduction392
5.7 Crosscutting Issues395
5.8 Putting It All Together: Multicore Processors and Their Performance400
5.9 Fallacies and Pitfalls405
5.10 Concluding Remarks409
5.11 Historical Perspectives and References412
Case Studies and Exercises by Amr Zaky and David A. Wood412
Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism432
6.1 Introduction432
6.2 Programming Models and Workloads for Warehouse-Scale Computers436
6.3 Computer Architecture of Warehouse-Scale Computers441
6.4 Physical Infrastructure and Costs of Warehouse-Scale Computers446
6.5 Cloud Computing: The Return of Utility Computing455
6.6 Crosscutting Issues461
6.7 Putting It All Together: A Google Warehouse-Scale Computer464
6.8 Fallacies and Pitfalls471
6.9 Concluding Remarks475
6.10 Historical Perspectives and References476
Case Studies and Exercises by Parthasarathy Ranganathan476