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Chapter 1 BASIC STRUCTURE OF COMPUTERS1

1.1 Computer Types2

1.2 Functional Units3

1.2.1 Input Unit4

1.2.2 Memory Unit4

1.2.3 Arithmetic and Logic Unit5

1.2.4 Output Unit6

1.2.5 Control Unit6

1.3 Basic Operational Concepts7

1.4 Bus Structures9

1.5 Software10

1.6 Performance13

1.6.2 Basic Performance Equation14

1.6.1 Processor Clock14

1.6.3 Pipelining and Superscalar Operation15

1.6.4 Clock Rate16

1.6.5 Instruction Set:CISC and RISC16

1.6.6 Compiler17

1.6.7 Performance Measurement17

1.7 Multiprocessors and Multicomputers18

1.8 Historical Perspective19

1.8.1 The First Generation19

1.8.2 The Second Generation20

1.8.3 The Third Generation20

1.8.4 The Fourth Generation20

1.8.5 Beyond the Fourth Generation21

1.8.6 Evolution of Performance21

1.9 Concluding Remarks21

Problems22

References23

Chapter 2 MACHINE INSTRUCTIONS AND PROGRAMS25

2.1 Numbers,Arithmetic Operations,and Characters27

2.1.1 Number Representation27

2.1.2 Addition of Positive Numbers28

2.1.3 Addition and Subtraction of Sigued Numbers29

2.1.4 Overflow in Intege rArithmetic32

2.1.5 Characters33

2.2 Memory Locations and Addresses33

2.2.1 Byte Addressability33

2.2.2 Big-endian and Little-endian Assignments35

2.2.4 Accessing Numbers,Characters,and Character Strings36

2.3 Memory Operations36

2.2.3 Word Alignment36

2.4 Instructions and Instruction Sequencing37

2.4.1 Register Transfer Notation37

2.4.2 Assembly Language Notation38

2.4.3 Basic Instruction Types38

2.4.4 Instruction Execution and Straight-Line Sequencing42

2.4.5 Branching44

2.4.6 Condition Codes46

2.4.7 Generating Memory Addresses47

2.5 Addressing Modes48

2.5.1 Implementation of Variables and Constants49

2.5.2 Indirection and Pointers50

2.5.3 Indexing and Arrays52

2.5.4 Relative Addressing56

2.5.5 Additional Modes56

2.6 Assembly Language58

2.6.1 Assembler Directives59

2.6.2 Assembly and Execution of Programs62

2.6.3 Number Notation64

2.7 Basic Input/Output Operations64

2.8 Stacks and Queues68

2.9 Subroutines72

2.9.1 Subroutine Nesting and the Processor Stack73

2.9.2 Parameter Passing74

2.9.3 The Stack Frame75

2.10 Additional Instructions81

2.10.1 Logic Instructions81

2.10.2 Shift and Rotate Instructions82

2.11.1 Vector Dot Product Program86

2.11 Example Programs86

2.10.3 Multiplication and Division86

2.11.2 Byte-Sorting Program87

2.11.3 Linked Lists89

2.12 Encoding of Machine Instructions94

2.13 Concluding Remarks98

Problems98

Chapter 3 ARM,MOTOROLA,AND INTEL INSTRUCTION SETS103

Part Ⅰ The ARM Example104

3.1 Registers,Memory Access,and Data Transfer104

3.1.1 Register Structure105

3.1.2 Memory Access Instructions and Addressing Modes106

3.1.3 Register Move Instructions113

3.2 Arithmetic and Logic Instructions113

3.2.1 Arithmetic Instructions113

3.2.2 Logic Instructions115

3.3 Branch Instructions116

3.3.1 Setting Condition Codes117

3.3.2 A Loop Program fof Adding Numbers118

3.4 Assembly Language118

3.4.1 Pseudo-Instructions120

3.5 I/O Operations121

3.6 Subroutines122

3.7 Program Examples126

3.7.1 Vector Dot Product Program126

3.7.2 Byte-Sorting Program127

3.7.3 Linked-List Insertion and Deletion Subroutines127

Part Ⅱ The 68000 Example130

3.8.2 Addressing131

3.8.1 The 68000 Register Structure131

3.8 Registers and Addressing131

3.9 Instructions136

3.10 Assembly Language140

3.11 Program Flow Control141

3.11.1 Condilion Code Flags141

3.11.2 Branch Instructions141

3.12 I/O Operations145

3.13 Stacks and Subroutines146

3.14 Logic Instructions151

3.15 Program Examples152

3.15.1 Vector Dot Product Program152

3.15.2 Byte-Sorting Program153

3.15.3 Linked-List Insertion and Deletion Subroutines154

Part Ⅲ The IA-32 Pentium Example155

3.16.1 IA-32 Register Structure156

3.16 Registers and Addressing156

3.16.2 IA-32 Addressing Modes159

3.17 IA-32 Instructions164

3.17.1 Machine Instruction Format168

3.18 IA-32 Assembly Language170

3.19 Program Flow Control171

3.19.1 Conditional Jumps and Condition Code Flags171

3.19.2 Unconditional Jump173

3.20 Logic and Shift/Rotate Instructions173

3.20.1 Logic Operations173

3.20.2 Shift and Rotate Operations173

3.21 I/O Operations174

3.21.1 Memory-Mapped I/O174

3.21.2 Isolated I/O175

3.21.3 Block Transfers176

3.22 Subroutines177

3.23 Other Instructions182

3.23.1 Multiply and Divide Instructions182

3.23.2 Multimedia Extension(MMX)Instructions183

3.23.3 Vector(SIMD)Instructions184

3.24 Program Examples184

3.24.1 Vector Dot Product Program184

3.24.2 Byte-Sorting Program185

3.24.3 Linked-List Insertion and Deletion Subroutines185

3.25 Concluding Remarks188

Problems188

References201

Chapter 4 INPUT/OUTPUT ORGANIZATION203

4.1 Accessing I/O Devices204

4.2 Interrupts208

4.2.1 Interrupt Hardware210

4.2.2 Enabling and Disabling Interrupts211

4.2.3 Handling Multiple Devices213

4.2.4 Controlling Device Requests217

4.2.5 Exceptions218

4.2.6 Use of Interrupts in Operating Systems220

4.3 Processor Examples224

4.3.1 ARM Interrupt Structure224

4.3.2 68000 Interrupt Structure229

4.3.3 Pentium Interrupt Structure231

4.4 Direct Memory Access234

4.4.1 Bus Arbitration237

4.5 Buses240

4.5.1 Synchronous Bus241

4.5.2 Asynchronous Bus244

4.5.3 Discussion247

4.6 Interface Circuits248

4.6.1 Parallel Port248

4.6.2 Serial Port257

4.7 Standard I/O Interfaces259

4.7.1 Peripheral Component Interconnect(PCI)Bus261

4.7.2 SCSI Bus266

4.7.3 Universal Serial Bus(USB)272

4.8 Concluding Remarks283

Problems283

References289

Chapter 5 THE MEMORY SYSTEM291

5.1 Some Basic Concepts292

5.2.1 Internal Organization of Memory Chips295

5.2 Semiconductor RAM Memories295

5.2.2 Static Memories297

5.2.3 Asynchronous Drams299

5.2.4 Synchronous DRAMs302

5.2.5 Structure of Larger Memories305

5.2.6 Memory System Considerations307

5.2.7 Rambus Memory308

5.3 Read-Only Memories309

5.3.1 ROM310

5.3.2 PROM311

5.3.3 EPROM311

5.3.4 EEPROM311

5.3.5 Flash Memory312

5.4 Speed,Size,and Cost313

5.5 Cache Memories314

5.5.1 Mapping Functions316

5.5.2 Replacement Algorithms321

5.5.3 Example of Mapping Techniques322

5.5.4 Examples of Caches in Commerciai Processors325

5.6 Performance Considerations329

5.6.1 Interleaving330

5.6.2 Hit Rate and Miss Penalty332

5.6.3 Caches on the Processor Chip334

5.6.4 Other Enhancements335

5.7 Virtual Memories337

5.7.1 Address Translation339

5.8 Memory Management Requirements343

5.9 Secondary Storage344

5.9.1 Magnetic Hard Disks344

5.9.2 Optical Disks352

5.9.3 Magnetic Tape Systems358

5.10 Concluding Remarks359

Problems360

References366

Chapter 6 ARITHMETIC367

6.1 Addition and Subtraction of Signed Numbers368

6.1.1 Addition/Subtraction Logic Unit369

6.2 Design of Fast Adders371

6.2.1 Carry-Lookahead Addition372

6.3 Multiplication of Positive Numbers376

6.4 Signed-Operand Multiplication380

6.4.1 Booth Algorithm380

6.5 Fast Multiplication383

6.5.1 Bit-Pair Recoding of Multipliers384

6.5.2 Carry-Save Addition of Summands385

6.6 Integer Division390

6.7 Floating-Point Numbers and Operations393

6.7.1 IEEE Standard for Floating-Point Numbers394

6.7.2 Arithmetic Operations on Floating-Point Numbers398

6.7.3 Guard Bits and Truncation399

6.7.4 Implementing Floating-Point Operations400

6.8 Concluding Remarks403

Problems403

References410

Chapter 7 BASIC PROCESSING UNIT411

7.1 Some Fundamental Concepts412

7.1.1 Register Transfets415

7.1.2 Performing an Arithmetic or Logic Operation415

7.1.3 Fetching a Word from Memory418

7.1.4 Storing a Word in Memory420

7.2 Execution of a Complete Instruction421

7.2.1 Branch Instructions422

7.3 Multiple-Bus Organization423

7.4 Hardwired Control425

7.4.1 A Complete Processor428

7.5 Microprogrammed Control429

7.5.1 Microinstructions432

7.5.2 Microprogram Sequencing435

7.5.3 Wide-Branch Addressing437

7.5.4 Microinstructions with Next-Address Field440

7.5.5 Prefetching Microinstructions443

7.5.6 Emulation443

7.6 Concluding Remarks445

Problems446

Chapter 8 PIPELINING453

8.1 Basic Concepts454

8.1.1 Role of Cache Memory456

8.1.2 Pipeline Performance458

8.2 Data Hazards461

8.2.1 Operand Forwarding462

8.2.2 Handling Data Hazards in Software464

8.2.3 Side Effects464

8.3 Instruction Hazards465

8.3.1 Unconditional Branches466

8.3.2 Conditional Branches and Branch Prediction470

8.4 Influence on Instruction Sets476

8.4.1 Addressing Modes476

8.4.2 Condition Codes478

8.5 Datapath and Control Considerations479

8.6 Superscalar Operation481

8.6.1 Out-of-Order Execution483

8.6.2 Execution Completion485

8.6.3 Dispatch Operation486

8.7 UltraSPARC Ⅱ EXAMPLE486

8.7.1 SPARC Architecture487

8.7.2 UltraSPARC Ⅱ493

8.7.3 Pipeline Structure493

8.8 Performance Considerations503

8.8.1 Effect of Instruction Hazards504

8.8.2 Number of Pipeline Stages505

8.9 Concluding Remarks506

Problems506

Reference509

Chapter 9 EMBEDDED SYSTEMS511

9.1 Examples of Embedded Systems512

9.1.1 Microwave Oven512

9.1.2 Digital Camera514

9.1.3 Home Telemetry516

9.2 Processor Chips for Embedded Applications517

9.3 A Simple Microcontroller518

9.3.1 Parallel I/O Ports518

9.3.2 Serial I/O Interface521

9.3.3 Counter/Timer523

9.3.4 Interrupt Control Mechanism525

9.4 Programming Considerations525

9.4.1 Polling Approach526

9.4.2 Interrupt Approach529

9.5 I/O Device Timing Constraints531

9.5.1 C Program for Transfer via a Circular Buffer533

9.5.2 Assembly Language Program for Transfer via a Circular Buffer534

9.6 Reaction Timer-An Example535

9.6.1 C Program for the Reaction Timer537

9.6.2 Assembly Language Program for the Reaction Timer537

9.6.3 Final Comments541

9.7 Embedded Processor Families541

9.7.1 Microcontrollers Based on the Intel 8051542

9.7.2 Motorola Microcontrollers542

9.7.3 ARM Microcontrollers543

9.8 Design Issues544

9.9 System-on-a-Chip546

9.9.1 FPGA Implementation547

9.10 Concluding Remarks549

Problems550

References552

Chapter 10 COMPUTER PERIPHERALS553

10.1 Input Devices554

10.1.1 Keyboard554

10.1.2 Mouse555

10.1.3 Trackball,Joystick,and Touchpad556

10.1.4 Scanners557

10.2 Output Devices558

10.2.1 Video Displays558

10.2.2 Flat-Panel Displays559

10.2.3 Printers560

10.2.4 Graphics Accelerators561

10.3 Serial Communication Links563

10.3.1 Asynchronous Transmission566

10.3.2 Synchronous Transmission568

10.3.3 Standard Communications Interfaces571

10.4 Concluding Remarks574

Problems575

Chapter 11 PROCESSOR FAMILIES577

11.1 The ARM Family579

11.1.1 The Thumb Instruction Set579

11.1.2 Processor and CPU Cores580

11.2 The Motorola 680X0 and ColdFire Families582

11.2.1 68020 Processor582

11.2.2 Enhancements in 68030 and 68040 Processors584

11.2.4 The ColdFire Family585

11.3 The Intel IA-32 Family585

11.2.3 68060 Processor585

11.3.1 IA-32 Memory Segmentation586

11.3.2 Sixteen-Bit Mode588

11.3.3 80386 and 80486 Processors588

11.3.4 Pentium Processor589

11.3.5 Pentium Pro Processor589

11.3.6 Pentium Ⅱand Ⅲ Processors590

11.3.7 Pentium 4 Processor590

11.3.8 Advanced Micro Devices IA-32 Processors591

11.4 The PowerPC Family591

11.4.1 Register Set591

11.4.2 Memory Addressing Modes592

11.4.3 Instructions592

11.4.4 PowerPC Processors592

11.5 The Sun Microsystems SPARC Family594

11.6.1 Instruction and Addressing Mode Formats596

11.6 The Compaq Alpha Family596

11.6.2 Alpha 21064 Processor597

11.6.3 Alpha 21164 Processor597

11.6.4 Alpha 21264 Processor597

11.7 The Intel IA-64 Family598

11.7.1 Instruction Bundles598

11.7.2 Conditional Execution598

11.7.3 Speculative Loads600

11.7.4 Registers and the Register Stack600

11.7.5 Itanium Processor602

11.8 A Stack Processor603

11.8.1 Stack Structure604

11.8.2 Stack Instructions606

11.8.3 Hardware Registers in the Stack610

Problems612

11.9 Concluding Remarks612

References614

Chapter 12 LARGE COMPUTER SYSTEMS617

12.1 Forms of Parallel Processing619

12.1.1 Classification of Parallel Structures619

12.2 Array Processors620

12.3 The Structure of General-Purpose Multiprocessors622

12.4 Interconnection Networks624

12.4.1 Single Bus624

12.4.2 Crossbar Networks625

12.4.3 Multistage Networks626

12.4.4 Hypercube Networks628

12.4.5 Mesh Networks630

12.4.6 Tree Networks630

12.4.7 Ring Networks631

12.4.8 Practical Considerations632

12.4.9 Mixed Topology Networks636

12.4.10 Symmetric Multiprocessors636

12.5 Memory Organization in Multiprocessors637

12.6 Program Parallelism and Shared Variables638

12.6.1 Accessing Shared Variables640

12.6.2 Cache Coherence641

12.6.3 Need for Locking and Cache Coherence645

12.7 Multicomputers645

12.7.1 Local Area Networks646

12.7.2 Ethemet(CSMA/CD)Bus646

12.7.3 Token Ring647

12.7.4 Network of Workstations647

12.8.1 Shared Memory Case648

12.8 Programmer's View of Shared Memory and Message Passing648

12.8.2 Message-Passing Case651

12.9 Performance Considerations653

12.9.1 Amdahl's Law654

12.9.2 Performance Indicators656

12.10 Concluding Remarks656

Problems657

References660

APPENDIX A:LOGIC CIRCUITS661

A.1 Basic Logic Functions662

A.1.1 Electronic Logic Gates665

A.2 Synthesis of Logic Functions666

A.3 Minimization of Logic Expressions668

A.3.1 Minimization Using Karnaugh Maps671

A.4 Synthesis with NAND and NOR Gates674

A.3.2 Don't-Care Conditions674

A.5 Practical Implementation of Logic Gates678

A.5.1 CMOS Circuits681

A.5.2 Propagation Delay686

A.5.3 Fan-In and Fan-Out Constraints687

A.5.4 Tri-state Buffers687

A.5.5 Integrated Circuit Packages688

A.6 Flip-Flops690

A.6.1 Gated Latches690

A.6.2 Master-Slave Flip-Flop694

A.6.3 Edge Triggering694

A.6.4 T Flip-Flop697

A.6.5 JK Flip-Flop697

A.6.6 Flip-Flops with Preset and Clear698

A.7 Registers and Shift Registers699

A.8 Counters702

A.9 Decoders703

A.10 Multiplexers705

A.11 Programmable Logic Devices(PLDs)705

A.11.1 Programmable Logic Array(PLA)707

A.11.2 Programmable Array Logic(PAL)710

A.11.3 Complex Programmable Logic Devices(CPLDs)711

A.12 Field-Programmable Gate Arrays712

A.13 Sequential Circuits714

A.13.1 An Example of an Up/Down Counter714

A.13.2 Timing Diagrams718

A.13.3 The Finite State Machine Model719

A.13.4 Synthesis of Finite State Machines720

Problems724

A.14 Concluding Remarks724

References731

APPENDIX B:ARM INSTRUCTION SET733

B.1 Instruction Encoding734

B.1.1 Arithmetic and Logic Instructions734

B.1.2 Memory Load and Store Instructions741

B.1.3 Block Load and Store Instructions744

B.1.4 Branch and Branch with Link Instructions747

B.1.5 Machine Control Instructions747

B.2 Other ARM Instructions750

B.2.1 Coprocessor Instructions750

B.2.2 Versions v4 and v5 Instructions750

B.3 Programming Experiments750

APPENDIX C:MOTOROLA 68000 INSTRUCTION SET751

APPENDIX D:INTEL IA-32 INSTRUCTION SET769

D.1 Instruction Encoding770

D.1.1 Addressing Modes772

D.2 Basic Instructions773

D.2.1 Conditional Jump Instructions782

D.2.2 Unconditional Jump Instructions782

D.3 Prefix Bytes782

D.4 Other Instructions783

D.4.1 String Instructions783

D 4.2 Floating-Point,MMX,and SSE Instructions784

D.5 Sixteen-Bit Operation785

D.6 Programming Experiments785

APPENDIX E:CHARACTER CODES AND NUMBER CONVERSION789

E.1 Character Codes790

E.2 Decimal-to-Binary Conversion793

INDEX795